[Scummvm-git-logs] scummvm master -> 34664be3d35734a9e6f2ccaaf111af9c66a8bcb1

[sluicebox]

This automated email contains information about 1 new commit which have been
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Summary:
34664be3d3 SCI32: Fix modulo opcode in SCI2.1Late and SCI3


Commit: 34664be3d35734a9e6f2ccaaf111af9c66a8bcb1
    https://github.com/scummvm/scummvm/commit/34664be3d35734a9e6f2ccaaf111af9c66a8bcb1
Author: sluicebox (22204938+sluicebox at users.noreply.github.com)
Date: 2022-08-29T03:25:31-07:00

Commit Message:
SCI32: Fix modulo opcode in SCI2.1Late and SCI3

Fixes LSL7 ocean motion, bug #10270

Changed paths:
    engines/sci/engine/vm_types.cpp


diff --git a/engines/sci/engine/vm_types.cpp b/engines/sci/engine/vm_types.cpp
index 17de3b1fca8..517778b781b 100644
--- a/engines/sci/engine/vm_types.cpp
+++ b/engines/sci/engine/vm_types.cpp
@@ -137,9 +137,16 @@ reg_t reg_t::operator%(const reg_t right) const {
 			warning("Modulo of a negative number has been requested for SCI0. This *could* lead to issues");
 		int16 value = toSint16();
 		int16 modulo = ABS(right.toSint16());
-		int16 result = value % modulo;
-		if (result < 0)
-			result += modulo;
+		int16 result;
+		if (getSciVersion() <= SCI_VERSION_2_1_MIDDLE) {
+			result = value % modulo;
+			if (result < 0)
+				result += modulo;
+		} else {
+			// SCI2.1 Late and SCI3 treat the dividend as unsigned.
+			// LSL7 ocean motion depends on this. Bug #10270
+			result = (uint16)value % modulo;
+		}
 		return make_reg(0, result);
 	} else
 		return lookForWorkaround(right, "modulo");